1. Field of the Invention. The present invention relates to clamping sense amplifiers for bipolar Random Access Memories (RAM) which prevent the lower potential, or most negative, bit line from going to too low a level during a "read" operation, since this could cause the selected cell to be written falsely.
2. Background Art
In conventional designs, a separate switchable clamp voltage is used to prevent the lower potential bit line from going too far negative. However, it is difficult to match this voltage with all the cells in the array. If the clamp voltage is too high on a given cell no output, or a weak output, will be is sensed. If the clamp voltage is too low false writing in a cell may occur. The clamping sense amplifier of the present invention does not require a separately controlled voltage for the RAM, since a clamp voltage referenced to itself is generated and used separately by each cell.
The conventional way to build a Bipolar Memory(RAM) cell is shown in FIG. 1. It consists of a cross coupled latch with load impedance, Z, to develop a voltage swing, dual emitter transistors with one pair connected together, and the other two connected to bit lines for reading and writing, pull down currents to discharge the bit lines, a current source for the cell, and a point for connecting to the Row Select line. The load impedance circuit, Z, can be either a resistor, a Schottky diode, or a network combining the two, or PNP transistors. The current source may be shared with the other memory cells connected to the same row driver.
A memory cell may be one which is sensed and written on a single pair of bit lines by use of extra emitters on the cell transistors. Since the emitters on the cell transistors can only charge the bit lines positive, a negative current is needed to discharge the bit line and distinguish between a high and low emitter. For a fast read access time, this negative current must be great enough to discharge the rather large capacitance on the bit line in a short time, and it usually is larger than the memory cell current which is kept low to minimize total power. It is also possible to switch this negative current to only the digit line to be selected for a read or write operation. Since this discharge current is larger than the cell current, if not properly controlled, it can write into a selected cell during a read operation, causing erroneous operation.
In conventional designs, this is prevented by applying a clamp voltage on the bit lines which prevents them from going too negative. This clamp voltage must be accurately controlled to be somewhere between the high and low levels of the two emitters, which are determined by the storage of a 1 or 0 in the cell. Also, the clamp voltage must be switched off during a write cycle. Due to the voltage drops on the Row line, component variations, etc., it is difficult to generate an accurate clamp voltage. Furthermore, when a given cell is selected by the raising of its Row line, no sense or read current can be observed until the cell output emitter voltage exceeds the clamp voltage, thereby increasing the read access time .